Fractionally-spaced equalizer for a DS-CDMA system

ABSTRACT

An adaptively-tuned filter (80) for use within the receiver (14) of a multiple-access code division (CDMA) communication system permits spectrally-inefficient transmissions to be made from each transmitter (12) used with such system, thereby simplifying the transmitter circuits, yet still achieves a signal-to-noise ratio (SNR) that approaches the SNR achieved when spectrally-efficient transmissions are made. The adaptive filter (80) also compensates for signal distortions resulting from multiple signal paths. The receiver (14) includes RF receiving circuits (60, 62), a matched filter (64), downconversion circuits (66, 68, 92), sampling circuits (70, 71, 72), a time acquisition circuit (76), an adaptive filter (80), a decimator circuit (75), a despreader circuit (77), and an accumulator circuit (78). The adaptive filter (80) includes, e.g., two LMS gradient filters (96a, 96b), or equivalent, that operate independently in parallel, with an accurate bit decision being used to select the tap signals to be used as the starting point for the next bit. The filters (80, 96) function as a fractionally-spaced chip-MSE equalizer that improves the bit-SNR in the presence of sufficient multi-access noise, and also provides narrowband noise rejection.

BACKGROUND OF THE INVENTION

The present invention relates to multiple-access communication systems,and more particularly to a multiple-access communication system thatutilizes a direct-sequence code-division multiple-access (DS-CDMA)approach, thereby allowing a multiplicity of separate transmitters toefficiently access a stationary base-station receiver.

Multiple-access communication systems are typically designed for usewith a relatively large number of separate transmitters (e.g., portableor mobile transmitters) that interface with at least one stationaryreceiver at one or more designated receiving locations. Suchmulti-access systems are commonly used with digital cellular telephones,personal communication services, wireless local area networks (LAN's),and the like. Because the receiver(s) of such systems must allow accessto a large number of users, each having a transmitter, some means mustbe used to efficiently interconnect the multiple transmitters to thereceiver(s), i.e., to efficiently utilize the available channelspectrum. Common techniques used to allow such multiple access includefrequency division multiple access (FDMA), time division multiple access(TDMA), and code-division multiple access (CDMA). The present inventionprovides multiple access through a CDMA-based communication system.

A simplified model of a CDMA system is as follows: a common carrierfrequency, modulated with data having a known bit time, is transmittedto a common receiver from each of several transmitters. All of thetransmitters share the same carrier frequency. Thus, all of thetransmitters may be tuned to the same RF frequency. Each transmitter hasits own low bandwidth information bearing signal having a prescribeddata rate or bit rate. This low bandwidth information signal ismultiplied by a unique high bandwidth signature waveform, which makes itpossible for the receiver to distinguish the desired signal from theother signals transmitted from the other transmitters. For purposes ofthe present application, it is assumed that the signature waveformconsists of a sum of time-offset copies of a waveform called the "chipwaveform." The signature waveform may be visualized as the result ofconvolving the chip waveform with a train of impulses, each of unit areaand of positive or negative polarity. The sequence of polaritiesincluded within the train of impulses is known in the art as a"spreading sequence" (or "spreading code"). The spreading sequence isunique to each transmitter, but the chip waveform is the same. If, as iscommon in the art, the spreading sequences appear statistically likerandom binary sequences, then the power spectrum of the resultingsignature sequence is substantially the same as that of the originalchip waveform. Thus, each transmitter sends a waveform of similar powerspectrum over the channel, and a receiver which has knowledge of aspreading sequence used by a transmitter can distinguish the signal sentby that transmitter on that basis. The unit of time between impulses inthe impulse train described above is known as a "chip time", T_(c) andthe reciprocal of this time is known as the "chip rate". The presentinvention is not limited to the above model of DS-CDMA, but thedescription is simplified by such a model.

A common problem facing all multiple-access communication systems isaccurately detecting the transmitted signal at the receiver after thesignal has passed through a noisy channel, i.e., after the transmittedsignal has been corrupted with noise. Such noise may include signalsfrom other transmitters, thermal noise, or noise from other sources. Ameasure of the ability to accurately detect a signal in a noisyenvironment is the signal-to-noise ratio (SNR), defined as the ratio ofthe power of the desired signal divided by the power of all otherundesired signals, measured at the final signal which is used to make adecision about the information bearing signal. A high SNR indicates thatthe integrity of the signal, when received at the receiver, has beenmore or less preserved, thereby enabling the individual bits of thesignal to be detected above the noise with a low probability of error.It is thus a common objective of any communication system, includingmultiple-access communication systems, to achieve a high SNR, despitethe noisy channels and mediums through which the transmitted signal maytraverse as it propagates from the transmitter to the receiver.

In a DS-CDMA system, the transmitted signal is not only subject toadditive white Gaussian noise (AWGN), a common form of noise in mostcommunication channels, but is also subject to "multiple-access noise",i.e., noise resulting from the presence of other users who aretransmitting at the prescribed carrier frequency and bit rates, but withdifferent signature waveforms. To minimize the effect of the AWGN, it isknown in the art to implement the receiver of a DS-CDMA system as afilter matched to the signature waveform of the user (transmitter) ofinterest. Unfortunately, such matched filter, while optimum forminimizing probability of bit error in AWGN, performs poorly whensignificant multiple-access noise is present. Thus, what is needed is atype of filter for use within a DS-CDMA receiver that performsacceptably in the presence of significant multiple-access interference.

An optimum multi-user receiver that minimizes multi-user noise is known.However, such optimum multi-user receiver is extremely complex. Numeroussub-optimal simplifications of such optimal structure have beenproposed, however, such "simplifications" still require locking anddespreading of some or all of the interfering signals, and hence alsorepresent substantially complex circuitry. Thus, the matched filterreceiver, despite its limitations, represents the most common method inpractice.

Another form of channel distortion frequently encountered withmultiple-access communication systems are signal reflections, or havingthe same signal traverse multiple paths as it arrives at the receiver.Channel distortion caused by multiple paths is commonly dealt with inthe prior art by utilizing a RAKE receiver. The term "RAKE" receiver hasbeen coined in the art, to describe the finite length impulse trainwhich results from such receiver when an impulse is applied to theinput. The impulse response, when graphed, looks like the teeth of agarden rake.) A RAKE receiver includes a delay line, or a series ofdelay elements, with signal taps being provided after each delay. Thetapped signals are then appropriately combined with other signals,through feedback and feedforward connections, in order to minimize theeffects of channel distortion.

The main source of noise in a typical CDMA system is multiple-accessnoise, which has a power spectrum similar to that of the signal ofinterest. Thus, a RAKE receiver must have signal taps spaced such thatthis power spectrum is flat (uncorrelated) when aliased at the tap rate.Such a limitation may significantly encumber the operation of the RAKEreceiver, especially when there is significant excess bandwidth (i.e., asignificantly non-flat transmitted power spectrum). This is especiallylikely to be the case for high bandwidth CDMA systems, owing to thedifficulty of generating a flat-spectrum chip waveform at very highrates. What is needed, therefore, is an improved receiver that performsthe function of the RAKE receiver, thereby compensating for channeldistortion, but which does so without the tap spacing limitations of theprior an RAKE receivers.

SUMMARY OF THE INVENTION

The present invention provides a DS-CDMA system that advantageouslyaddresses the above and other needs. A DS-CDMA communication system madein accordance with the invention includes a multiplicity of transmittersand at least one receiver. Each transmitter transmits its outgoingDS-CDMA signal using a spectrally inefficient power spectrum, i.e., anon-flat power spectrum, thereby simplifying the circuitry used withinthe transmitter, and allowing the transmitter to be less expensive andsmaller than spectrally-efficient CDMA transmitters. The receiverreceives the transmitted CDMA signal and operates thereon on abit-by-bit basis, i.e., bit decisions are based on observation of thereceived waveform over approximately one bit time in the absence ofknowledge of the other users' (transmitters') spreading codes, chiptiming, and carrier phase.

The receiver includes a matched filter and an adaptive linear filter.The matched filter is designed to have a frequency response that matchesthe power spectrum of the transmitted CDMA signal. The adaptive linearfilter is configured to make the SNR for the spectrally-inefficientsignature waveforms received from the transmitter approachasymptotically the SNR that would be received from aspectrally-efficient transmitted signal, at high signal to thermal noiseratios. Advantageously, because CDMA systems typically operate in asituation of high multiple-access noise and low thermal noise, thisasymptotic result may be nearly realized in practice. Hence, the DS-CDMAsystem of the present invention advantageously simplifies the task ofthe transmitter (allowing transmission of spectrally-inefficientsignature waveforms) while attaining a SNR performance nearly as good asspectrally-efficient spreading of the same bandwidth. Further, the useof the adaptive linear filter makes the system highly resistant tonarrowband noise.

In accordance with one aspect of the invention, the adaptive linearfilter utilized by the DS-CDMA receiver is a discrete time filter. Theincoming RF signal, after passing through the matched filter, isdownconverted in quadrature, providing a complex series signal. Thecomplex series signal is then passed through the adaptive linear filter.Such filter advantageously allows the SNR to be nearly maximized whenthe number of CDMA users (i.e., the number of transmitters) is large(more than about 5 to 10). The adaptive filter includes a sequence ofdelay elements that delay the incoming signal by a prescribed amount.The delay may be a one-sample delay, thereby facilitating implementationof the adaptive filter using a digital processor. In other embodiments,the delay may be realized using an analog delay line, in which case thedelay provided is for a fixed time increment. Signal tap points areprovided after each delay, and the delayed signal from each tap, as wellas the incoming signal, are multiplied by appropriate "tap weight"signals, or tap coefficients, and then summed. The tap coefficients areadaptively adjusted, using feedforward and feedback components of theincoming and delayed signals, so as to produce the set of tapcoefficients that approximately maximize the average SNR.

In accordance with a further aspect of the invention, the tapcoefficients of the linear filter are adaptively tuned in a way thatcompensates for distortion, e.g., caused by multiple signal paths, thatoccurs in the transmitted signal en-route to the receiver.

In accordance with yet another aspect of the invention, a minimumchip-MSE (mean square error) equalizer, or a fractionally spacedequalizer, is utilized to improve the bit-SNR in a system withsufficient multiple access noise.

In accordance with still another aspect of the invention, two paralleladaptive linear filters may operate simultaneously, one assumingpositive data and the other negative. Such parallel configuration thusdoes not require that reliable chip decisions be available. At the endof a bit time, a bit decision selects a set of tap signals that willserve as the starting point for the next bit.

In accordance with another aspect of the invention, after the signal haspassed through the adaptive linear filter, at a rate which is defined bythe sampling or delay period of the filter, the filtered signal isdecimated by an appropriate factor to yield a series signal (at a ratedefined by the chip rate) that enables the chip sequence included withinthe bit interval to be discerned. The chip sequence is then despread andsummed to provide an output signal from which an appropriate decisionstatistic for the bit interval can be rendered.

Thus, one embodiment of the invention may be characterized as adirect-sequence multiple-access code division (DS-CDMA) communicationsystem. Such system includes a multiplicity of separate transmitters andat least one base-station receiver. Each of the mobile transmittersincludes: (a) means for producing a unique binary spreading sequence;(b) means for generating from such binary spreading sequence a uniquesignature waveform, said unique signature waveform having a bandwidthsubstantially corresponding to an allowed channel bandwidth, and anon-flat power spectrum which rolls gradually at the band edges; (c)means for generating a low bandwidth analog baseband waveform signalencoded with digital data that is to be transmitted; (d) means formultiplying the unique signature waveform with the low bandwidth analogbaseband waveform to yield a direct sequence spread waveform signal; (e)means for modulating a common RF carrier signal with the direct sequencespread waveform signal; and (f) means for transmitting the modulated RFcarrier signal.

The base-station receiver of such communication system comprises: (a)means for receiving the transmitted modulated RF carrier signals fromeach of the multiplicity of transmitters, including matched filter meansand quadrature downconversion means, (b) adaptive filter means forfiltering the modulated RF carrier signal to maximize the SNR,compensate for the non-flat power spectrum of the signature waveform,and compensate for signal distortions, (c) despreading means to despreadthe filtered signal in order to identify a particular signature waveformcontained therein, and (d) an integrator, or summing means, to integratesuch signal over a bit time to determine the informational contentthereof, i.e., whether such integrated signal represents a logical "1"or a "0".

The adaptive filter means, which forms a key element of the invention,includes a sampling circuit connected to sample the waveform signal,after downconversion, at a specified sampling rate, e.g., the Nyquistrate. Because the downconversion occurs in quadrature, such samplingcircuit provides a complex signal at its output (i.e., a signal havingreal and imaginary components). The adaptive filter then receives thesampled complex waveform signal and generates a filtered output signaltherefrom as a function of a specified transfer function. The specifiedtransfer function compensates for the non-flat power spectrum of theselected one of the transmitted waveform signals and also compensatesfor channel distortions that may distort the transmitted waveform signalwhile en-route to the receiver.

Another embodiment of the invention may be characterized as an adaptivefilter for use within a receiver of a CDMA communication system thatincludes first and second fractionally-spaced equalizers, each of whichoperates independent of the other to make a bit decision. One of the bitdecisions is selected as the correct bit decision, and the tap signalsfrom such equalizer are then used to influence the bit decision to bemade for the next bit.

It is thus a feature of the present invention to provide a simplifiedDS-CDMA system that achieves a high SNR, despite the noisy channels andmediums through which the transmitted signal traverses as it propagatesfrom the transmitter to the receiver, and despite signal or channeldistortion that may be present due, e.g., to multiple signal paths.

It is an additional feature of the invention to provide a DS-CDMAreceiver that utilizes one or more fractionally spaced equalizercircuits on a chip level to compensate for spectral inefficiency,implement a non-aliasing RAKE, and reject narrowband noise.

It is another feature of the invention to provide such a DS-CDMA systemthat simplifies the transmitter circuits by eliminating the need forflat-spectrum pulses, and instead allows a transmitted pulse shape witha rounded spectrum.

It is a further feature of the invention to provide such a simplifiedDS-CDMA system that includes a receiver which compensates for aspectrally-inefficient shape of the transmitted pulse, whichcompensation provides a SNR that approximates that which could beobtained using a spectrally-efficient shape.

It is an additional feature of the invention to provide an adaptivefilter for use within a DS-CDMA receiver that performs acceptably in thepresence of significant multi-access noise.

It is another feature of the invention to provide a receiver for usewithin a CDMA system that uses a minimum chip-MSE equalizer to improvebit-SNR in the presence of sufficient multiple access noise.

It is an additional feature of the invention to provide a CDMA receiverthat performs the multipath mitigation function of a RAKE receiver, butwhich does so before aliasing occurs.

It is yet another feature of the invention to provide a practical,economical DS-CDMA receiver structure that nearly maximizes the SNR,improves the probability of error, is highly resistant to narrowbandnoise, and makes bit decisions based on observation of the receivedwaveform over one bit time in the absence of knowledge of the otherusers' (transmitters') spreading codes, chip timing, and carrier phase.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and advantages of the presentinvention will be more apparent from the following more particulardescription thereof, presented in conjunction with the followingdrawings wherein:

FIG. 1 illustrates the concept of mobile-to-base communications utilizedby a DS-CDMA communication system;

FIG. 2 functionally depicts the concept of code-division multiple access(CDMA); showing how a CDMA signal made up of a plurality of chips at achip time T_(c) is used within each bit time, T_(B), of a data signal;

FIG. 3A conceptually illustrates a spectrally efficient power spectrumfor use by a CDMA transmitter, as is commonly used in the prior art; anda

FIG. 3B illustrates a spectrally inefficient power spectrum, as is usedby the present invention;

FIG. 4 is a simplified functional block diagram of a CDMA transmitter;

FIG. 5 is a simplified functional block diagram of a CDMA receiver;

FIG. 6 conceptually illustrates the result achieved by the inventionrelative to the frequency domain performance of a communication systemmade in accordance with the present invention, and in particularillustrates how an adaptive filter, identified as A(e^(j)ω), used withinthe receiver compensates for the spectrally inefficient performance ofthe transmitter;

FIG. 7 depicts a model of the CDMA transmitter of the present invention;

FIG. 8 illustrates a model of the CDMA receiver of the presentinvention;

FIG. 9 shows a block diagram of a CDMA system made in accordance withthe present invention;

FIG. 10 shows a block diagram that shows the internal detail of one ofthe LMS gradient filters of FIG. 9; and

FIG. 11 depicts how complex signals are multiplied within an adaptivefilter made in accordance with the present invention.

Corresponding reference characters indicate corresponding componentsthroughout the several views of the drawings.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best mode presently contemplated forcarrying out the invention. This description is not to be taken in alimiting sense, but is made merely for the purpose of describing thegeneral principles of the invention. The scope of the invention shouldbe determined with reference to the claims.

Referring first to FIG. 1, there is shown a communications system 10that includes a plurality of mobile transmitter units 12-1, 12-2, . . .12-k (any one of which may hereafter be referred to as the transmitter12 or transmitter unit 12), and a single base-station receiver 14. Eachof the transmitter units 12 is configured to transmit a signal that ismodulated in accordance with a code-division multiple access (CDMA)scheme, as explained more fully below. The transmitted CDMA signalspropagate, along respective signal paths 16-1, 16-2, . . . 16-k(referred to generically hereafter as the signal path 16), through atransmission medium 18, and are received at the base-station receiver14. The transmission medium 18 may also be referred to as thecommunication channel. While a single signal path may exist from eachtransmitter 12 through the medium 18 to the base-station receiver 14, itis not uncommon for multiple signal paths to exist, e.g., due toreflections of the transmitted signal, such as the signal path 16'-1 inFIG. 1. As a result, a given transmitted signal may arrive at thebase-station 14 through different signal paths. Such different signalpaths may introduce significant channel distortion of transfer functionD(ω) into the signal received at the base-station receiver. The presentinvention advantageously recognizes when such signal distortion ispresent and acts accordingly.

For many applications, the transmitter units 12 are mobile, as in adigital cellular telephone system. Hence, hereafter the system 10 may bereferred to as a mobile-to-base station communication system. However,it is to be understood such description is only exemplary and that thetransmitter units 12 need not be mobile.

The medium (or channel) 18 introduces noise into the transmitted signalsreceived at the base-station 14. Additionally, there may be narrowbandinterference from a nearby narrowband communications system, or fromhostile jamming. A major source of interference in a CDMA system isnoise from other users of the system, known in the art asmultiple-access interference. An important feature of the receiver 14 ofthe present invention is to alleviate the effects of suchmultiple-access noise, and to be highly resistant to narrowband noise,as well as to increase the signal-to-noise ratio (SNR) so that thetransmitted signals can be detected at the receiver 14 with a lowprobability of error.

All efficient communication systems, such as the mobile-to-base stationsystem shown in FIG. 1, utilize some technique for maximizing thechannel efficiency, i.e., for maximizing the number of users (i.e.,transmitter units) that may communicate through the system 10 withoutinterfering with each other. As indicated in the above backgrounddiscussion, many different "multiple use" schemes are known in the art.Such multi-access schemes include, for example, frequency divisionmultiple access (FDMA) wherein each user is assigned a differenttransmission frequency; time division multiple access (TDMA), whereineach user transmits a signal that occupies a different time slot orspace; and code-division multiple access (CDMA), wherein each usertransmits a signal at the same frequency and time, but wherein eachinformation-bearing signal is further encoded with a unique signaturewaveform. The communication system 10 of the present invention utilizesa CDMA scheme, and is particularly suited for a CDMA scheme thatoperates at a high data rate, although the invention may be used withany CDMA scheme, e.g., a CDMA-based cellular telephone system.

The basic concept of CDMA modulation is taught with respect to FIG. 2.Shown in the upper portion of FIG. 2 is a data waveform 20 that includesa plurality of bit times, T_(B). For purposes of FIG. 2, the waveform 20is shown as a function of time and amplitude, with time being thehorizontal axis, and amplitude being the vertical axis. The waveform 20thus includes a sequence of data bits, each of duration T_(B), with eachbit being either a digital "1" or a "0". A sequence of bits of aprescribed length (number of bits) is referred to as a digital "word".Typically, for most digital communication systems, a sequence of digitaldata words must be transmitted in a prescribed format in order toidentify a particular user, and in order to provide other control andmanagement information. For example, a cellular telephone system usuallyrequires that each mobile transmitter transmit several informationalwords, each of a known or prescribed length, e.g., 48 bits. Even voicesignals that are transmitted from the mobile transmitters to thebase-station receiver once acquisition has been achieved and all thenecessary control and management signals have been sent, may beconverted to digital words prior to transmission. The waveform 20 thuscomprises the low bandwidth information bearing signal. Only twocomplete bits of such information bearing signal are shown.

For clarity, the digital waveform 20 shown in FIG. 2 is depicted in anNRZ (non-return-to-zero) format (where a logical "1" maps to a -1normalized amplitude, and a logical "0" maps to a+1 normalizedamplitude). It is to be understood, however, that such representation isonly exemplary. In practice, the information bearing signal 20 may beencoded in any appropriate manner, e.g., with Manchester (biphase)encoding, in order to shift the power spectral density of thetransmitted waveform away from zero, or for other purposes.

In a CDMA scheme, each bit of the digital waveform 20 is furthersubdivided into a plurality of "chip times", T_(c), as shown in thelower portion of FIG. 2. Typically, there is a large number of chiptimes within each bit. About 127 to 255 chips per bit is typical. Thesignature waveform consists of a square-wave binary waveform signal 21which assumes the value of +1 or -1 in each chip-time interval T_(c).The value assumed by the signature waveform during each interval T_(c)is determined by the successive values of the binary spreading sequence(code) for a particular user. The signature waveform 21 is multiplied bythe information bearing signal 20 to yield a direct sequence spreadwaveform 22.

For the example shown in FIG. 2, there are ten chips per bit. A chipwaveform 23 comprises a rectangular (in time) pulse of duration T_(c)and amplitude 1. The signature waveform signal 21 is obtained byrepeating the chip waveform 23 at T_(c) intervals, each occurrence beingmultiplied by successive elements of the spreading code {+1, -1, +1, +1,-1, -1,+1, -1, +1, -1}, with the spreading code being repeated each bittime T_(B). The information bearing signal 20 is multiplied by thesignature waveform 22 to yield the direct sequence spread waveform.Thus, when the data bit is a logical "1" (or a -1 amplitude as shown inFIG. 2), the direct sequence spread waveform 22 comprises the inverse ofthe signature waveform 21. When the dam bit is a logical "0" (or a "+1"amplitude as shown in FIG. 2), the direct sequence spread waveform 22 isthe same as the signature waveform 21.

Each separate transmitter 12 (FIG. 1) is configured to uniquely encodeeach bit time with a particular signature waveform. Such signaturewaveform thereafter serves to uniquely identify the bit as havingoriginated from a particular transmitter. Thus, when multipletransmitters are used, and multiple bits are thus in the transmissionmedium at any given time, each bit carries its own unique signaturewaveform, which unique signature waveform may be considered as an"identification tag" that identifies the particular transmitter fromwhich the bit originated. The presence of such "identification tag"thereafter conceptually provides a means for sorting all the bitsreceived at the base-station receiver 14 so that the receiver processingcircuits can determine which received bit signals came from whichtransmitters, thereby enabling multiple users to use the system at thesame time.

A significant advantage of a CDMA-based system is that the transmitterunits may operate asynchronously. Asynchronous operation significantlyreduces the complexity of the transmitter circuits as compared, e.g.,with a TDMA-based system where careful synchronization between all ofthe transmitters is required. Moreover, in a CDMA-based system, thetransmitter units 12 may all operate at the same carrier frequency.Hence, the individual transmitter units 12 need not be individuallytuned to a specific operating frequency, and can share the sametransmission bandwidth with other transmitter units. Such bandwidthsharing and avoidance of individual tuning significantly reduces thecost of manufacturing and maintaining the mobile transmitter units 12.The present invention retains this important advantage of a CDMA-basedsystem.

The present invention further simplifies the design, and hence the costof manufacture and maintenance, of each transmitter unit 12 in that thetransmitter unit 12 need not operate in a spectrally efficient manner.As explained previously, spectrally-efficient CDMA systems haveheretofore transmitted their direct sequence spread waveform using afiat power spectrum in order to improve the SNR of the received signal,e.g., by using signature waveforms constructed as shown in FIG. 2, wherethe chip waveform is a sinc shape, with a rectangular spectrum occupyingthe entire allowed band. To transmit fiat-spectrum pulses requires theuse of output circuitry within the transmitter unit, e.g., an outputfilter, that has a frequency response substantially as shown in FIG. 3A.Disadvantageously, such output circuitry, if optimum, is very complexand expensive.

Perhaps the chief disadvantage of the fiat-spectrum chip waveform is itsduration in the time domain. It can be shown that the inverse Fouriertransform h(t) of a frequency response H(ω) as shown in FIG. 3A onlydecays as 1/t. Thus, each pulse is significantly different from 0 over alarge number of chip intervals T_(c) in both directions from the center.This complicates the production of an accurate approximation of h(t).For example, for low bandwidth spread systems, a reasonable method ofproducing h(t) is to use a digital finite impulse response (FIR) filterwith an impulse response shaped like h(t) but sampled at fractions ofT_(c). The result, when passed through a suitable digital-to-analog(D/A) converter looks like h(t) with stair-step edges, which stair-stepedges may then be filtered off. However, the duration of the digital FIRfilter must be large to generate an accurate representation of h(t)because of the pulse's long duration in the time domain. Thus, longduration in the time domain of the chip pulse is a significantdisadvantage, and use of the digital FIR filter is limited to low chiprates.

In contrast to the spectrally efficient transmission of flat-spectrumchip waveforms in prior CDMA transmitter units, the present inventionutilizes a spectrally inefficient transmission, having a rounded shapeas shown generally in FIG. 3B. Such spectrally inefficient transmissionmay be realized, e.g., by using a digital circuit to generatesquare-wave chips, (where a "chip" is defined here to be thespreading-code modulated chip waveform, with T_(c) as the chip time),and then passing the chips through an analog low-pass filter with cutoffat the first spectral null of the square-wave. Such a transmitter isextremely simple and can operate at chip rates in excess of 100 MHz.Further, due to its simplicity, such a transmitter is significantly lessexpensive.

A simplified functional block diagram of a CDMA transmitter unit 12 thattransmits in a spectrally inefficient manner in accordance the presentinvention is shown in FIG. 4. It is to be emphasized that such diagramis functional in nature, and that the individual blocks included in suchblock diagram may, in practice, be realized in numerous ways and forms,including dedicated hardware circuits, adaptive hardware circuitscontrolled by firmware, processor circuits controlled by a suitablecontrol program (software control), or combinations of such hardware,firmware and software.

As seen in FIG. 4, the transmitter unit 12 need only include anoscillator 26 that generates a basic clock signal at a rate 1/T_(c) fromwhich the bit time T_(B) can be derived. Typically, the oscillator 26operates at the chip time, so that the period of the oscillator is thechip period, T_(c). The clock signal generated by the oscillator 26 thusdrives a chip generator 28, with the chip generator 28 being configuredto generate a chip waveform signal 22 that is unique to the transmitter12. A memory 27 (which may be included as part of the chip generator 28,but is shown separately in FIG. 4 for clarity), or equivalent circuitry,contains the spreading code from which the signature waveform signal 21is derived. The clock signal generated by the oscillator 26 is alsodivided by an integer N_(c) by a dividing circuit 30, where N_(c) =TB/TCrepresents the number of chips per bit. The resultant signal, afterdivision by N_(c), is then used to drive a data generator 32. The datagenerator 32 is modulated with a suitable data source in order togenerate an information bearing signal 20.

The signature waveform signal 21 output from the chip generator 28 isthen multiplied by the information bearing signal 20 output from thedata generator 32 using a suitable multiplier circuit 42, or equivalentmodulator. Where the signature waveform signal 21 and the informationbearing signal are digital logic signals that assume values of "1" or"0" to represent the binary signal, a simple modulator may be realizedusing an Exclusive OR gate. Where the signature waveform signal 21 andthe information bearing signal are signals that assume values of "+1"and "-1" to represent binary data, as shown in FIG. 2, then a simplemodulator is a multiplying circuit.

Once the signature waveform signal 22 has been incorporated into theinformation bearing signal 33 through the modulation circuitry 42, theresulting combined signal is passed through a suitable low pass filter(LPF) 44 having a cutoff frequency at the first spectral null of thechip pulse generator signal. The output of this LPF has a rounded powerspectrum in the band ±1/T_(c), shaped as the main lobe of a sinc-squaredfunction, and is thus spectrally-inefficient (S.I.) as discussed above.Such S.I. signal, which is now an analog signal, modulates an RF carriersignal, generated by an RF generator 46, in conventional manner using aconventional RF modulator circuit 48. Typically, some form of digitalmodulation may be used, such as DSB-AM (double side band amplitudemodulation), which may be realized in its simplest form by multiplyingthe sequence by the RF carrier. Other types of modulation may also beused. The resulting signal is passed through a band-pass filter (BPF)50, to remove unwanted side-bands, amplified in a power amplifier 52,and then transmitted through a suitable broadcast antenna 54. Thetransmitted signal, S.sup.(k) (t), is thus an RF signal modulated withthe information bearing signal 20, each bit of which is furthermodulated with the chip waveform signal 21.

Referring next to FIG. 5, a simplified functional block diagram of thebase-station receiver 14 is depicted. The base-station receiver 14includes a suitable receiving antenna 60 through which the transmittedsignal s.sup.(k) (t) is received. Such received signal is firstamplified and filtered using an RF amplifier 62. Next, the amplified RFsignal is applied to a matched filter 64.

The matched filter circuit 64 is designed to match the frequencyresponse of the incoming spectrally inefficient chip waveform includedin each bit of the information bearing signal 20 included within theincoming signal s.sup.(k) (t). Thus, the frequency response of thematched filter 64 has a general rounded shape, as shown in FIG. 3B. Thedesign of the matched filter 64 may be conventional.

Next the filtered signal is downconverted in order to remove the carrierfrequency therefrom. Assuming a carrier frequency of ω_(c),downconversion is accomplished by splitting the filtered signal into twoparallel signal paths. In a first signal path, the signal is multipliedby cos(ω_(c) t) in a multiplier element 66. In a second signal path, thesignal is multiplied by sin(ω_(c) t) in a multiplier element 68. As isknown in the art, such multiplication creates upper and lower sidebands,the lower sideband of which represents the incoming signal with thecarrier frequency stripped therefrom. Hence, appropriate anti-aliasingfilters 67 and 69 remove the unwanted sidebands, leaving the desiredinformation bearing signal transmitted from the transmitter unit 12.Such filters 67 and 69 should have a cutoff frequency of ±1/(2T_(H)),thereby providing a total bandwidth of 1/T_(H), which is defined as thechannel bandwidth. In the frequency domain, the shape of theanti-aliasing filters 67 and 69 is rectangular, with unit gain between-1/(2T_(H)) and +1/(2T_(H)), and zero elsewhere.

Downconversion in the manner depicted in FIG. 5 is referred to asquadrature downconversion, and the resulting downconverted signal is acomplex signal, i.e., two signals having a specific phase relationshipto each other. Mathematically, such downconversion can be modeled asyielding a complex signal, having real and imaginary components. Thereal component corresponds to the signal being processed along onesignal path, and the imaginary component corresponds to the signal beingprocessed along the other signal path.

After downconversion, both signals, i.e., both components of the complexsignal, are sampled at an appropriate sampling rate, e.g., at least theNyquist rate. Thus, one signal path includes a sampler 70 that samplesthe signal every kT_(H) seconds, and the other signal path likewiseincludes a sampler 72 that samples the signal every kT_(H) seconds. Itis assumed here that 1/T_(H) is an integer multiple of 1/Tc. Suchsampled signals thus create a complex set of series signals referred toas x_(i). For simplicity, hereafter, references to the parallelquadrature paths in the receiver will be made as though they were asingle complex-valued signal. However, it is to be understood that suchsignals must physically consist of two separate real-valued signalspassed along separate signal paths. In FIG. 5, such separate signalpaths are shown as two parallel signal paths 74.

The sampled signal x_(i) is directed to both an adaptive filter 80,having a transfer function A(e^(j)ω), and to a time acquisition circuit76. The time acquisition circuit 76 extracts timing information from thesignal x_(i), and produces a synchronized signal that controls thesamplers 70 and 72, and produces a correctly aligned spreading code, forsubsequent use by a despreader circuit 77, explained below.

The adaptive filter 80, which forms a key part of the present invention,compensates for the spectrally inefficient signature waveform. The netresult is that SNR of the received signal, after being processed by theadaptive linear filter 80, approaches asymptotically the SNR that wouldbe received from a spectrally-efficient transmitted signature waveformsignal, assuming a high signal to thermal noise ratio (which is usuallythe case for a CDMA system).

Conceptually, the above advantage of having the SNR approach the SNRthat would be received from a spectrally-efficient signature waveformsignal is achieved by making the frequency-domain response of theadaptive linear filter, referred to herein as A(e^(j)ω), assume a "U"shape, as shown in FIG. 6. The net result of having such a U-shapedfrequency-domain response, as also shown in FIG. 6, is that itcompensates for the spectrally-inefficient response of the transmittedsignal, thereby rendering the power spectrum of the signal output fromthe adaptive filter substantially flat. A substantially flat response,in turn, maximizes the SNR, as is known in the art.

The adaptive filter 80 further compensates for signal distortions thatoccur in the signal x_(i) as it traverses through the noisy medium 18(FIG. 1). The output of the adaptive filter 80 is a series signal Y_(i).The adaptive filter 80 is described more fully below in conjunction withFIGS. 9 and 10.

The output series from the adaptive filter 80 is decimated at anappropriate rate, 1/D, where D=T_(c) /T_(H), to yield an output seriesat the rate 1/T_(c), assuming that T_(H) is as defined above. If thetransmitted chip waveform is spectrally inefficient, then its bandwidthis usually greater than 1/T_(c), because there is normally some excessbandwidth. Hence, sampling must occur at a rate faster than 1/T_(c) iffiltering is going to occur without aliasing. It is a feature of thepresent invention that sampling can occur without aliasing. However, theoutput z_(n) has to occur at the chip rate 1/T_(c) so it can becorrelated with c_(n), the spreading code. To accomplish this result,the filter output y_(i) must be decimated by 1/D, i.e., D-1 of every Dsamples must be thrown out. Such decimation is provided by a suitabledecimator device 75. As a result, the decimated signal z_(n) has N_(c)values every bit, where N_(c) is defined as T_(B) /T_(C).

After decimation has occurred, the signal is despread in a despreadercircuit 77. The despreader circuit 77 is coupled to the time acquisitioncircuitry 76, as mentioned above. The correctly aligned spreading codefor a user of interest is applied to the despreader circuit 77. When thesignal is properly aligned with the signal of interest, which alignmentis achieved by adjusting the time when the sampling if done by thesamplers 70 and 72, it identifies where within the signal the bit timesstart and stop for the user of interest. Once despread, the signal issummed over the bit time using a summation circuit 78 that yields afinal bit signal G[p], which signal may be used as a decision statisticto determine whether the p^(th) transmitted bit was a "1" or a "0".

It is noted that the simplicity of the transmitter 12 achieved by thepresent invention comes at the cost of somewhat increased complexitywithin the receiver 14, such increased complexity being manifest by theinclusion of the adaptive linear filter 80. Advantageously, the "frontend" of the receiver 14 shown in FIG. 5 may be a common front end usedby all the incoming signals from the numerous transmitters. Such frontend includes the antenna 60, RF amplifier 62, matched filter 64, anddownconverters 66 and 68. A separate "back end" of the receiver 14 wouldthen be used for each transmitter of interest, where the back endincludes the samplers 70 and 72, time acquisition circuitry 76, adaptivefilter 80, decimator 75, despreader 77, and summer 78. In this way,multiple signals generated from multiple transmitters may be processedat the same time. Advantageously, because there are generally many moretransmitters 12 than receivers 14, reducing the complexity of thetransmitter (by allowing spectrally inefficient transmission) at thecost of additional complexity in the receiver (by addition of theadaptive filter) reduces the overall total system complexity and cost.

It is also noted that the receiver circuits (FIG. 5) may be realized inmany forms. For example, each of the circuits included within thereceiver 14 may be constructed from dedicated hardware circuits,comprising integrated circuits, transistors, resistors, capacitors,inductors, and other electronic components. Alternatively, the functionsperformed by some of the circuits can readily be carried out using asuitable processor circuit, e.g., a microprocessor circuit, controlledby a suitable control program. Moreover, for some applications, somefunctions included within the receiver circuits may be carried out usingdedicated hardware circuits, and others may be carried out using anappropriately programmed processor circuit. It is submitted that thoseof skill in the art, given the description presented herein of thefunctions performed by such circuits and the inter-relationship betweensuch circuits, can readily fashion such circuitry, whether realizedusing dedicated hardware circuits, programmed logic circuits, programmedprocessor circuits or combinations thereof.

Before describing the adaptive filter 80 in more detail, and in order tobetter understand the present invention, reference is next made to FIGS.7 and 8 where there is shown a model of a transmitter and receiver,respectively, of the type that are used with the present invention. FIG.7 depicts the model of the kth transmitter 12, assuming there are K CDMAusers accessing the particular channel of interest. FIG. 8 depicts themodel of the kth receiver.

The kth users' data bits, d_(i).sup.(k) belonging to the set {+1, -1}are defined such that ##EQU1## where p_(T) (t)=1 for t between 0 and T,and 0 elsewhere. The impulse generator 84 generates a train of impulsesof unit area, with the polarity of each impulse determined by successiveelements of the spreading code c_(i).sup.(k). These impulses aregenerated at the rate 1/T_(C), where the number of chips per bit, N_(C)(=T_(B) /T_(C)), is an integer. A sequence b_(i).sup.(k) which belongsto the set {+1 , -1}, is defined as the spreading code times the data,d.sup.(k) (t-τ_(k)), such that

    b.sub.i.sup.(k) =c.sub.i.sup.(k) c.sub.i/Nc.sup.(k)        (1)

where the term x within the brackets indicates the integer portion of x.Using this definition, it can be seen that the output of the multiplier86 is another impulse train, given by Σb_(i).sup.(k) δ(t-iT_(c) -τ_(k)).This signal passes through a filter 88 having a transfer function H(ω).The filter H(ω) determines the chip waveform. Thus, for example, thesystem of FIG. 5 corresponds to the case where H(ω) is the Fouriertransform of the chip waveform P_(Tc) (t), illustrated as waveform 23 inFIG. 2. After passing through the filter 88, the resulting signal ismultiplied by an amplitude constant A, and modulated with an RF carrierfrequency ω_(c), such that the k^(th) transmitted signal, s.sup.(k) (t),is given by ##EQU2## where h(t) is the inverse Fourier transform ofH(ω). It is assumed that the transmission system is band limited by theconstraint ##EQU3## for some constant T_(H). Note that T_(H) is distinctfrom the time between the starts of successive chip waveforms, T_(c). Itis assumed that T_(c) =DT_(H) for some integer D. The integer D is thusthe number of time periods T_(H) per chip time T_(c). The terms τ_(k)and θ_(k) are random variables that represent delays and phases that areindependent and uniformly distributed in the region [0,T_(c) ] and[0,2π], respectively.

Turning next to FIG. 8, a model of the k^(th) receiver is shown. Thetransmitted signal s.sup.(k) (t) has the AWGN and the interference I(t)from the other channels added thereto, as represented by the summingblock 90. The resultant signal, r(t), received at the receiver 14 duringthe interval [0, T_(B) ], assuming the constant A is perceived at thereceiver to be at the same level from each of the K transmitters, hasthe form

    r(t)=s.sup.(1) (t)+I(t)+n.sub.ω (t),                 (4)

where n_(w) (t) is the additive white Gaussian noise (AWGN) of two-sidedspectral density η₀ /2, s.sup.(1) (t) is the desired signal term, andI(t) is the interference due to the K-1 additional users of the channel.Such interference may be expressed as ##EQU4## where it has beenassumed, without loss of generality, that user 1 is the signal ofinterest.

For purposes of the model given in FIG. 8, the signal is thendownconverted, as represented by the multiplier 92 and the signal2cos(ω_(c) t+θ_(k)), and passed through a chip matched filter 94. Thechip matched filter 94 has a frequency-domain response of H*(ω),designed to match the response H(ω) of the transmitter. The output ofthe chip matched filter is then sampled with a suitable sampler 95, atthe Nyquist rate (t=mT_(H) +τ_(k)), in order to yield a series x_(m).

The series x_(m) is applied to an adaptive linear filter 96. Theadaptive linear filter 96 is a two-sided finite impulse response (FIR)filter having L taps per side. Such filter has tap coefficients {α_(-L),. . . α_(L) } such that its discrete-time transfer function that may beexpressed as ##EQU5## where α_(n) are the tap coefficients.

The output y_(m) of the filter 96 is decimated by a factor 1/D to yielda series z_(n) (at a rate 1/T_(C)). Such series in then despread, bymultiplying it by the known chip sequence c_(n).sup.(k) using themultiplier circuit 98. Assuming that the signal c_(n).sup.(k) isproperly aligned with the signal of interest, it will correlate withhigh magnitude (with polarity determined by the information bearingsignal) with the signal from the k^(th) transmitter, and correlate withsmall magnitude with the signals from the other K-1 transmitters,thereby facilitating detection of the signal of interest. Once despread,the signal is summed over the bit time using an appropriate summationcircuit 100 to yield a final bit signal G[p], which signal may be usedas a decision statistic to determine whether the p^(th) transmitted bitwas a "0" or a "1".

The adaptive linear filter 96 (or the filter 80 in FIG. 5) may take manyforms, depending upon the particular application involved. For example,a suitable adaptive linear filter 96 that attains SNR performance nearlyas good as spectrally-efficient spreading, and that is highly resistantto narrowband noise, is disclosed in Applicant's copending patentapplication, filed concurrently herewith, Ser. No. 08/139,957, entitledA MULTIPLE-ACCESS NOISE REJECTION FILTER FOR A DS-CDMA SYSTEM. Suchcopending patent application is incorporated herein by reference,including the materials incorporated by reference therein. Suchmaterials include, which materials are also incorporated herein byreference, the following: (1) Davis et al., "Implementation of a CDMAReceiver with Multiple-Access Noise Rejection", IEEE Conference onPersonal, Indoor, and Mobile Radio Communications pp. 103-107 (pub. Oct.19, 1992); (2) Monk et al., "A Noise Whitening Approach toMultiple-Access Noise Rejection--Part I: Theory and Background (filed asAppendix A of the copending application); and (3) Davis et al., "A NoiseWhitening Approach to Multiple-Access Noise Rejection--Part II:Implementation Issues" (filed as Appendix B of the copendingapplication).

Turning next to FIG. 10, there is shown a block diagram of a CDMA systemmade in accordance with the present invention. As seen in FIG. 9, thesystem includes a downconverter 92, a matched filter 94, and a sampler71. These elements correspond to, and perform the same function as, thematched filter 64, downconverters 66 and 68, and samplers 70 and 72shown in FIG. 5. Note, the downconverter 92 in FIG. 9 is not shown as aquadrature downconverter. For simplicity, the carrier phase θ₁ isinstead assumed to be known by the receiver. This achieves the sameeffect.

The system shown in FIG. 9 also includes an adaptive filter 80 which ismade up of two LMS gradient filters 96a and 96b, operating in paralleland independent of each other. An LMS gradient filter, as is known inthe art, operates in iterative fashion. Essentially, each LMS gradientfilter receives a series x_(m) as an input, obtained from the samplercircuit 71. Each sample represents a new input signal. At the beginningof each bit time, each filter starts with a set of tap weight signals.Such tap weight signals operate on the input signal, x_(m), and at theconclusion of the bit time, a new set of tap weight signals have beengenerated. A multiplexer 140 selects one of the set of tap weightsignals from either the LMS gradient filter 96a or 96b as the startingtap weight signals for the next iteration. This process repeats over andover again.

To better understand the operation of the system of FIG. 9, reference isnext made to FIG. 10, where there is shown a more detailed diagram of anLMS gradient filter 96. Advantageously, use of such LMS gradient filters96a and 96b, or equivalent filters, allows the task of the transmitter12 to be simplified while attaining SNR performance nearly as good asspectrally-efficient spreading of the same bandwidth; is highlyresistant to narrowband noise; and performs the multipath mitigationfunction of a RAKE receiver, but does so before aliasing occurs.

The filter 96 provides a discrete time transfer function as expressed inEq. (6), where L represents the number of taps per side of the filter.As seen in FIG. 10, the filter 96 includes a series of 2L delayelements, 120a, 120b, 120c, 120d, each providing a delay of T_(H). Eachdelay element has an input signal line and an output signal line. Thesignal on the output signal line is delayed by T_(H) seconds from thesignal appearing at the input signal line. In a preferred embodiment ofthe invention, the delay T_(H) may be one-sample delay, and the delayelements may be realized using a shift register of length m, where m isthe number of delay elements used. However, it is to be understood thatin other embodiments, the delay may be a known delay of T_(H) seconds,as where, for example, the delay elements 120a, 120b, . . . 120n arerealized using an analog delay line.

The filter 96 in FIG. 10 illustrates a filter having L=2, thus there arefour delay elements 120. As seen in FIG. 10, the input signal line ofeach delay element, as well as the output signal line of the last delayelement, is coupled to a first series of multiplier elements 124. Thatis, the input signal line of delay element 120a is connected to one ofthe inputs of multiplier element 124a, the input signal line of delayelement 120b is connected to one of the inputs of multiplier element124b, and so on, with the output signal line of delay element 120d beingconnected to one of the inputs of multiplier element 124e. The otherinput of the multiplier element 124a is connected to the tap weightsignal α₋₂. Similarly, the other input of the multiplier element 124b isconnected to the tap weight signal, α₋₁ ; the other input of themultiplier element 124c is connected to the tap weight signal, α₀ ; theother input of the multiplier element 124d is connected to the tapweight signal, α₁ ; and the other input of the multiplier element 124eis connected to the tap weight signal, α₂. Thus, it is seen that for 2Ldelay elements in the filter 96, there are 2L+1 "tap signals" thatrepresent the contents of the 2L delay elements and the input signal.These 2L+1 tap signals are connected to 2L+1 multiplier elements usedwith the filter. The output of each of the 2L+1 multiplier elements,e.g., the output of elements 124a, 124b, 124c, 124d and 124e, isconnected to a summing circuit 126. As seen in FIG. 10, the 2L+1 delaysignals are also directed to respective tap processing networks 128a,128b, 128c, 128d, and 128e.

Each tap processing network 128a, 128b, 128c, 128d, and 128e includes,as seen in FIG. 9 for the network 128e, a first multiplier element 130,a second multiplier element 132, and a summer 134. The first multiplierelement 130 receives as one of its input signals the respective tapsignal. The other input signal of the first multiplier element 130 is anerror correction signal 136, described below. The output of the firstmultiplier element 130 of each network 128 is connected to one of theinputs of the second multiplier element 132. The other input of thesecond multiplier element 132 is connected to receive a constant signalΔ. The output of the multiplier element 132 is connected to an input ofthe summer 134. The summer 134 sums (i.e., accumulates) the signalapplied to its input every time the tap weight signals are updated. Suchsum represents the respective tap weight signal, α_(n). This updateinterval is ideally once every T_(c) seconds (every D input samples).Timing of the sampler 95 is adjusted by the time tracking provided bythe timing acquisition circuit 76 so that the iteration occurs when themaximum power point of a chip waveform h(t) is present in the desiredsignal at the center tap of the filter 96. However, the filter, beingfractionally spaced, is relatively insensitive to this timing. All thatis essential is that the update of the summer 134, which constitutes anupdate of the "tap weight", be performed at the rate 1/T_(c) or somefraction thereof.

The output of the summing circuit 126, designated as y_(i) in FIG. 10,is compared to a chip decision signal b_(n).sup.(1) a comparitor circuit138. The difference between y_(i) and b_(n).sup.(1) comprises the errorcorrection signal 136 referred to above that is looped back to each ofthe tap processing networks 128.

In operation, i.e., at each discrete time, a tap coefficient vector αmay be defined as |α_(-L), . . . , α_(L), |^(T). At time iT_(H), i.e.,each sample time, the contents of the delay line (sequence of delayelements 120) comprise a vector x[i]=|x_(i+L), . . . , x_(i-L) |^(T).Hence, if α^(n) represents the tap coefficients at the n^(th) iteration,the adaptive filter shown in FIG. 10 implements the adaptive algorithm

    α.sup.n+1 =α.sup.n +Δx[n]{b.sub.n.sup.(1) -(x.sub.T [n]α.sup.n)},                                       (7)

where b_(n).sup.(1) is the receiver's decision for the n^(th)data-modulated chip. Such algorithm may be implemented mathematicallyusing a suitable digital computer, or it may be implemented usingdiscrete circuits. When the parameter Δ is appropriately selected, Eq.(7) converges to the solution:

    R.sub.x α=h.sub.2.sup.D [0],                         (8)

    where

    R.sub.x =E{x[0]x.sup.T [0]}                                (9)

is the covariance matrix of the input signal, and where h^(D) ₂ [0] is avector of T_(H) spaced samples of the inverse Fourier transform of thedistorted pulse shape |H(ω)|² D(ω), where D(ω) represents the unforeseenchannel distortion. More specifically, if h₂ ^(D) (t) is the inverseFourier transform of |(H(ω)|² D(ω), then h₂ ^(D) [0] is the vector |h₂^(D) (-LT_(H)) . . . h₂ ^(D) (LT_(H))|^(T). Advantageously, the tapweights obtained from the adaptive algorithm expressed above in Eq. (8)approximately maximize an average expression for SNR when the number Kof CDMA users is large (more than about 5 to 10), as set forth in Davis,et al., "A Noise Whitening Approach to Multiple-Access NoiseRejection--Part II:Implementation Issues., supra. Further, the samestructure also rejects narrowband noise.

Moreover, it is noted that there exists a large amount of literaturethat shows how to adaptively solve matrix equations like Eq. (8) usingfilter structures and techniques that may be completely different fromthat shown in FIG. 10, but which are nonetheless equivalent thereto. Anysuch equivalent structures could be used by the present invention.

The signal Δ is typically a constant signal, which may be obtained froma suitable generator 127, or other source. As indicated, by properlyselecting Δ, the convergence rate of Eq. (7) is controlled.

Use of the adaptive algorithm of Eq. (7) raises two issues. First, in atypical CDMA system, accurate chip decisions b_(i).sup.(k) are notpossible. Second, because a specific user's signal is needed to generatean error signal, the algorithm shown in Eq. (7), unlike the algorithmshown in Eq. (7) of Applicant's copending application, cannot be rundirectly on an RF filter which serves a set of CDMA receivers at acommon site. Both of these problems are addressed by using a filterstructure as shown in FIG. 10.

As described briefly above, the filter structure shown in FIG. 9includes two parallel LMS gradient filters 96a and 96b, each of which isas described in FIG. 9. Since the spreading sequence is known to thereceiver, the data-modulated chips b.sup.(1)_(n) are known to either+c_(n).sup.(1) or -c_(n).sup.(1). Hence, each filter 96a and 96boperates independent of the other, one assuming that b_(i).sup.(k)=+c_(i).sup.(k), and the other assuming that b_(i).sup.(k)=-c_(i).sup.(k). At the end of a bit time, a bit decision is used toselect which set of tap signals, i.e., which set of 2L+1 tap signals,from the filter 96a or from the filter 96b will serve as the startingpoint for the next bit. Such bit decision is made by directing theoutput from each filter 96a and 96b, shown as signal lines 137a and137b, respectively, to appropriate bit decision circuitry. Dependingupon the bit decision that is made, a multiplexer 140 is controlled toselect the tap signals to be used as the starting point for the next bitdecision. The selected set of tap signals is applied to whichever filter96a or 96b does not already have such tap signals therein beforestarting processing of the next bit.

Bit decisions may be determined as follows: both filter outputs 137a and137b are despread by despreader 98 and summed by summer 100 to determinetwo decisions statistics. If each statistic indicates the same data bit,then that is the bit decision. If each indicates that the data bit wasthe assumed data bit (one filter assumes positive data, the othernegative), then the decision statistic of greater magnitude is chosen.If each indicates that the data bit was the opposite of the assumed databit, then that of smaller magnitude is chosen. If users 2 . . . Kexperience similar distortion, then the tap signals determined in FIG. 9are appropriate for all signals, and may be fed to an analog transversalfilter 142 as shown in FIG. 9. Otherwise, all K receivers must run theadaptive algorithm independently.

With the two issues mentioned above addressed through use of a filterstructure as is shown in FIG. 9, or equivalent structure, theequalization algorithm of Eq. (7) above offers significant advantagesover the algorithm expressed in Eq. (7) of Applicant's copendingapplication. In the copending application, the adaptive filter isdesigned to observe only the noise process. Thus, it assumes the shapeof the signal, and trains the filter accordingly. The adaptive filterdescribed herein, in contrast, uses the signal component within thereceived waveform as the basis for training the filter. Hence, if thereis unforeseen channel distortion D(ω), the arriving chip signals willhave Fourier transform D(ω)H(ω) instead of H(ω). The adaptive filterdescribed in the copending application will, in such instance, bematched to the wrong receive pulse shape. The adaptive filter describedherein, however, will automatically determine the received chip shapeand act accordingly. Thus, the equalization approach of the presentinvention is robust to unforeseen changes in the received pulse shape.

Moreover, it is noted that if the sample time is sufficient to sampleh(t) without aliasing, the matching filter H*(ω) may be dispensed withentirely, and the matching function will be automatically trained intothe equalizer. In addition, a fractionally-spaced equalizer, isrelatively insensitive to sample timing error. Hence, if the sample timeis not exactly synchronous with the chip times, the algorithm of Eq. (7)will still find the signal in the delay line and synthesize theappropriate corrective delay. That is, the adaptive filter of thepresent invention performs code tracking to some degree. Such advantageis not possible with the adaptive algorithm described in Applicant'scopending application, which must know the signal shape and timing apriori.

It is noted that the set of tap weight signals that maximize the SNR isprovided by an equation similar to Eq. (8) above, but where the matrixR_(x) on the left side contains only the noise terms, not the signal ofinterest. A key feature of the invention is the recognition that ifsignificant multiple-access interference is guaranteed to be present,i.e., if it is known that there will be more than 5 to 10 other users,then the solution to Eq. (8) is sufficiently close to the SNR-maximizingsolution, regardless of the thermal noise level.

It is further noted that when complex signal processing is carried outin the adaptive filter 80, that multiplication and addition of both ofthe signal components associated with such complex signal is required.Addition is straightforward. Multiplication is achieved, as shown inFIG. 11. As seen in FIG. 11, conventional (non-complex) multiplicationoccurs using a multiplier 150 that multiplies a first input signal by asecond input signal to yield an output signal. When the signals to bemultiplied are complex signals, four multipliers are required, 152, 154,156 and 158. Each input signal has two components. Each component isapplied to a respective one of the four multiplier elements. Thus, ifthe components of the complex signal on the first input line are a_(x)and a_(y), and if the components of the complex signal on the secondinput line are b_(x) and b_(y), then multiplier element 152 multipliesb_(x) ·a_(y), multiplier element 154 multiplies a_(y) ·b_(y), multiplierelement 156 multiplies a_(x) ·b_(x), and multiplier element 158multiplies a_(x) ·b_(y). The products of the multiplications performedby multipliers 154 and 156 are subtracted by subtraction element 160,and the products of the multiplications performed by multipliers 152 and158 are added by adder 162 to yield a new complex signal, c_(x), c_(y).

Thus, it is seen that the present invention provides a simplifiedDS-CDMA system that achieves a high SNR, despite the noisy channels andmediums through which the transmitted signal traverses as it propagatesfrom the transmitter to the receiver, and despite signal or channeldistortion that may be present due, e.g., to multiple signal paths. Itis further seen that such a DS-CDMA system significantly simplifies thetransmitter circuits by eliminating the need for flat-spectrum pulses,by using a receiver that compensates for the spectrally-inefficientshape of the transmitted pulse.

It is further seen that the present invention provides a receiver foruse within a CDMA system that uses a minimum chip-MSE equalizer toimprove bit-SNR in the presence of sufficient multiple access noise. Itis also seen that such CDMA receiver adaptively performs the multipathmitigation function of a RAKE receiver, but does so before aliasingoccurs.

While the invention herein disclosed has been described by means ofspecific embodiments and applications thereof, numerous modificationsand variations could be made thereto by those skilled in the art withoutdeparting from the scope of the invention set forth in the claims.

What is claimed is:
 1. A direct-sequence multiple-access code division(DS-CDMA) communication system comprising:a multiplicity oftransmitters, each of said transmitters including: means for generatinga CDMA waveform signal, said CDMA waveform signal comprising an RFcarrier signal modulated with an informational data signal comprising asequence of data bits, each data bit having a bit time of T_(B), andeach data bit being modulated with a waveform signature signal, saidwaveform signature signal comprising a train of N_(c) chip pulses, eachchip pulse being separated from an adjacent chip pulse by T_(c) secondssuch that N_(C) ·T_(C) =T_(B), each chip pulse of said train of chippulses having an amplitude set by a binary spreading code unique to eachtransmitter; means for transmitting the CDMA waveform signal from eachof said multiplicity of transmitters so that the chip pulses aretransmitted having a spectrally inefficient, substantially non-flat,power spectrum within the band ±1/T_(C) ; and a receiver comprising:means for receiving the CDMA waveform signals transmitted from each ofsaid multiplicity of transmitters and stripping the RF carrier signaltherefrom, thereby leaving a data input signal to said receiver thatcomprises said sequence of data bits, with each data bit being modulatedwith the waveform signature that is unique to each transmitter; samplingmeans for sampling the data input signal at a prescribed sampling rateto produce a series signal x_(m) ; adaptive filter means coupled toreceive said series signal x_(m) and subject it to a prescribed transferfunction that produces a filtered output signal y_(m), said transferfunction being adapted to compensate for the spectrally inefficientsubstantially non-flat power spectrum of the transmitted chip pulseswithin the band ±1/T_(C), thereby improving the signal-to-noise ratio(SNR) of the signal y_(m), and said transfer function further beingadapted to compensate the series signal x_(m) for signal distortionscaused by multiple signal paths of the CDMA waveform signal as it istransmitted from the transmitter to the receiver; decimator means fordecimating the filtered output signal y_(m) by a prescribed decimationfactor D to produce a decimated series signal z_(n) ; timing acquisitionmeans responsive to the series signal x_(m) for generating the binaryspreading code of a user of interest and a timing signal that controlswhen within a data bit of said data input signal the sampling meanssamples the data input signal; despreading means connected to saiddecimator means and responsive to said timing signal for identifying thebeginning and ending points of a data bit within said series signalz_(n) that originates with said user of interest by multiplying theseries signal z_(n) by an aligned spreading code c_(n) ; andaccumulation means for summing said series signal z_(n), as aligned bythe spreading code c_(n), over the data bit to produce a data decisionsignal.
 2. The DS-CDMA system as set forth in claim 1 wherein said meansfor receiving the CDMA waveform signals includes a matched filterthrough which the received CDMA signals pass, said matched filter havinga frequency response H*(ω) that matches the power spectrum of thetransmitted chip pulses.
 3. The DS-CDMA system as set forth in claim 2wherein said means for receiving the CDMA waveform signals furtherincludes quadrature downconversion means for stripping the RF carrierfrom the received CDMA system and producing first and second data inputsignals, the first data input signal containing one component of acomplex signal, and the second data input signal containing anothercomponent of the complex signal.
 4. The DS-CDMA system as set forth inclaim 3 wherein said sampling means comprises first and second samplingmeans, the first sampling means sampling the first data input signal,and the second sampling means sampling the second data input signal. 5.The DS-CDMA system as set forth in claim 1 wherein the means fortransmitting the CDMA waveform signal using a spectrally inefficientsubstantially non-flat power spectrum within the band ±1/T_(C)comprisesa square wave generator that generates a square wave having aperiod equal to said chip separation time, T_(C), and that modulatessaid square wave with said binary spreading code to produce saidwaveform signature, a low pass filter having a cut off frequency atabout 1/T_(C), said waveform signature being passed through said lowpass filter.
 6. The DS-CDMA system as set forth in claim 2 wherein theadaptive filter of said receiver includes a two-sided finite impulseresponse (FIR) filter of L taps per side.
 7. The DS-CDMA system as setforth in claim 6 wherein said adaptive filter includes first and secondFIR filters, each receiving the sampled input data signal, x_(m), andeach generating an signal y_(m) from which separate data decisionsignals may be generated, and each having feedback means for applying aset of starting tap signals to a selected one of said first or secondFIR filters at the beginning of a new bit processing time that is thesame as a set of ending tap signals present in the other of said firstor second FIR filters at the conclusion of a most recent bit processingtime.
 8. The DS-CDMA system as set forth in claim 7 wherein each of saidfirst and second FIR filters comprises a sequence of delay elements thatdelay an incoming signal by a prescribed amount, T_(H) ; a tap pointbeing provided on each side of each delay element; and further includinga series of multiplier elements that multiply a signal from each tappoint by a respective tap coefficient signal, with the resulting outputsignals from said multiplier elements being summed to produce saidfiltered output signal; and further including tap coefficient signalgenerating means for generating a set of tap coefficient signals inaccordance with a prescribed function of a tap point signal from arespective tap point, a control parameter Δ, and said filtered outputsignal; said prescribed function being selected to produce a set of tapcoefficient signals that maximize an average SNR of the signal y_(m). 9.The DS-CDMA system as set forth in claim 8 wherein said prescribedfunction used by said tap coefficient generating means to generate saidset of tap coefficient signals comprises Σ, summed over a prescribedperiod of time, where S₁ is the tap point signal appearing at arespective tap point, S₂ is said filtered output signal, and S₃ is saidcontrol parameter Δ.
 10. A direct-sequence multiple-access code division(DS-CDMA) communication system comprising:a multiplicity oftransmitters, each of said transmitters including: a CDMA waveformsignal generator that generates a CDMA waveform signal, said CDMAwaveform signal comprising an RF carrier signal modulated with a firstbandwidth informational data signal comprising a sequence of data bits,each data bit having a bit time of T_(B), and each data bit beingmodulated with a second bandwidth waveform signature signal, saidwaveform signature signal comprising a train of N_(C) chip pulses, eachchip pulse being separated from an adjacent chip pulse by T_(C) secondssuch that N_(C) ·T_(C) =T_(B), each chip pulse of said train of chippulses having an amplitude set by a binary spreading code unique to eachtransmitter; a transmitter that transmits the CDMA waveform signal fromeach of said multiplicity of transmitters so that the chip pulses aretransmitted having a spectrally inefficient substantially non-flat powerspectrum within a band ±1/T_(C) ; and a receiver comprising:an RFreceiver that receives the CDMA waveform signals transmitted from eachof said multiplicity of transmitters and strips the RF carrier signaltherefrom, thereby leaving a data input signal to said receiver thatcomprises said sequence of data bits, with each data bit being modulatedwith the waveform signature that is unique to each transmitter; asampling circuit that samples the data input signal at a prescribedsampling rate to produce a series signal x_(m) ; an adaptive filtercoupled to receive said series signal x_(m) and subject it to aprescribed transfer function that produces a filtered output signaly_(m), said transfer function being adapted to compensate for thespectrally inefficient substantially non-flat power spectrum of thetransmitted chip pulses within the band ±1/T_(C), and to compensate theseries signal x_(m) for signal distortions caused by multiple signalpaths of the CDMA waveform signal as it is transmitted from thetransmitter to the receiver;a decimator circuit that decimates thefiltered output signal y_(m) by a prescribed decimation factor D toproduce a decimated series signal z_(n) ; timing acquisition meansresponsive to the series signal x_(m) for generating the binaryspreading code of a user of interest and a timing signal that controlswhen within a data bit of said data input signal the sampling meanssamples the data input signal; a despreading circuit connected to saiddecimator circuit and responsive to said timing signal that identifiesthe beginning and ending points of a data bit within said series signalz_(n) that originates with said user of interest and that multiplies theseries signal z_(n) by an aligned spreading code c_(n) ; and anaccumulator that accumulates the series signal z_(n), as multiplied bythe spreading code c_(n), over the data bit to produce a data decisionsignal.
 11. A fractionally-spaced equalizer for use within a receiver ofa code-division multiple-access (CDMA) communication system, said CDMAcommunication system including a multiplicity of transmitters adapted totransmit data bit signals to said receiver, each transmitter of saidmultiplicity of transmitters having means for modulating its transmitteddata bits with a prescribed signature waveform, each transmitter furtherhaving its data bit signals transmitted having a spectrally inefficient,substantially non-flat, power spectrum within a band ±1/T_(C), whereT_(C) is a chip time associated with the prescribed signature waveform,said equalizer comprising:a series of 2L delay elements, where L is apositive integer, each for delaying an input signal applied to an inputport thereof by an amount T_(H), a first delay element having an inputport to which the input signal is applied, and an output port connectedto the input port of an adjacent delay element, whereby the input signalis delayed by a total delay of 2LT_(H) as it is passed through saidseries of delay elements from the first delay element to a second delayelement, from the second delay element to a third delay element, and soon, to the last delay element, each of said delay elements having a tappoint on both sides thereof, whereby 2L+1 tap points are provided; meansfor coupling a transmitted data bit signal received by said receiver tothe input port of the first delay element; a series of 2L+1 multiplierelements, each multiplier element of said series of 2L+1 multiplierelements having first and second input ports and an output port, withthe signal at the output port being the product of the signals appliedto the first and second input ports, the first input port of eachmultiplier element of said first series being connected to a respectivetap point; an accumulation circuit having 2L+1 input terminals and anoutput terminal, said accumulation circuit providing a sum signal at itsoutput terminal that is the sum of the signals applied to each of its2L+1 input terminals, said 2L+1 input terminals being connected to theoutput port of a corresponding one of said first series of 2L+1multiplier elements; a series of 2L+1 tap processing networks, eachnetwork of said series of 2L+1 tap processing networks having first,second, and third input terminals, and an output terminal, the outputterminal providing a signal that represents a prescribed function ofsignals applied to the first, second, and third input terminals, saidfirst input terminal being connected to the tap point of a respectiveone of said 2L+1 delay elements, the second input terminal beingconnected to an error signal, the third input terminal being connectedto a fixed control signal, and the output terminal being connected tothe second input port of a respective one of said first series of 2L+1multiplier elements; a difference circuit having a negative inputterminal, a positive input terminal, and an output terminal, adifference signal being provided at its output terminal that representsthe difference between a signal applied to the negative input terminaland a signal applied to the positive input terminal, the negative inputsignal of said difference circuit being connected to the output terminalof the summation circuit, the positive input terminal being connected toa signal representative of a prescribed chip waveform associated with aknown user of said CDMA system, and the output terminal being applied tothe second input terminal of each of said 2L+1 tap processing networks,the difference signal generated by said difference circuit therebycomprising said error signal; the signal appearing at the outputterminal of said accumulation circuit representing an output signal ofsaid fractionally-spaced equalizer; the combination of signals appearingat the respective output terminals of the 2L+1 tap processing networkscomprising a set of tap weight signals that adaptively tune saidfractionally-spaced equalizer to compensate for the spectrallyinefficient, substantially non-flat, power spectrum of the transmitteddata bit signals; and means for setting the fixed control signal appliedto the second input terminal of the 2L tap processing networks to avalue that maximizes the signal-to-noise ratio of the output signal. 12.The fractionally-spaced equalizer as set forth in claim 11 wherein saidmeans for coupling a transmitted data bit signal received by saidreceiver to the input port of the first delay means comprises:a matchedfilter through which the transmitted data bit signal passes, saidmatched filter having a frequency response adapted to match the powerspectrum of the transmitted data bit signal; and sampling means forsampling the transmitted data bit signal at a prescribed sampling rate,thereby producing a sampled series x_(m) that is applied to the inputport of the first delay means.
 13. The fractionally-spaced equalizer asset forth in claim 11 wherein said series of 2L delay means comprises adelay line having at least 2L+1 tap points, with the signal appearing ateach tap point being delayed T_(H) from the signal appearing at a priortap point.
 14. The fractionally-spaced equalizer as set forth in claim13 wherein said series of 2L delay means comprises a shift register oflength 2L, said shift register being clocked at a rate of 1/T_(H) so asto shift the contents held in each register to an adjacent registerevery T_(H) seconds.
 15. The fractionally-spaced equalizer as set forthin claim 11 wherein the prescribed function that defines the outputterminal of said tap processing networks as a function of the signalsapplied to the first, second, and third input terminals comprises Σ[(S₁×S₂)×S₃ ], accumulated over a prescribed period of time, where S_(i)represents the signal applied to the i^(th) input terminal.
 16. Thefractionally-spaced equalizer as set forth in claim 15 wherein theprescribed period of time over which the signals S_(i) are accumulatedin accordance with the prescribed function comprises a period of a databit within said data signal.
 17. An adaptive filter for use within areceiver of a code-division multiple-access (CDMA) communication system,said CDMA communication system including a multiplicity of transmitters,each adapted to transmit a data bit signal to said receiver, and eachtransmitter having means for modulating the individual bits of itstransmitted data bit signal with a prescribed chip waveform, and eachtransmitter further having its data bit signal transmitted having aspectrally inefficient, substantially non-flat, power spectrum within aband ±1/T_(C), where T_(C) is a chip time associated with the prescribedchip waveform, said adaptive filter comprising:first and second digitalfilters, each having a signal input port, a signal output port, an errorsignal port, and a set of signal tap ports, each further having meansfor processing an input signal applied to its input port in accordancewith a prescribed discrete transfer function to produce an updatedoutput signal as a function of prior signals present at its signaloutput port, error signal port, and signal tap ports, with the set ofsignal tap ports of each digital filter being adapted to compensate forthe spectrally inefficient, substantially non-flat, power spectrum ofthe transmitted data bit signal; first and second comparison circuits,each having a first input terminal, a second input terminal, and anoutput terminal, and each providing an error signal that appears at itsoutput terminal as a function of the relationship between signalsapplied to its first and second input terminals, the first inputterminal of each comparison circuit being connected to the output portof a corresponding one of said first and second digital filters, and theoutput terminal of each comparison circuit being connected to the errorsignal port of a corresponding one of said first and second digitalfilters, the second input terminals of each comparison circuit beingcoupled to a positive reference chip signal and a negative referencechip signal, respectively; a multiplexer circuit having first and secondsets of input terminals, a set of output terminals, and a controlterminal, with the set of output terminals being switchably connected toa selected one of the first or second sets of input terminals as afunction of a control signal applied to said control terminal, saidfirst and second sets of input terminals being connected respectively tothe first and second sets of signal tap ports of the first and seconddigital filters, and said set of output terminals also being connectedto the first and second sets of signal tap ports of both said first andsecond digital filters, whereby a selected one of the set of tap signalspresent in said first and second digital filters at the conclusion of aprocessing time interval is used by both of said first and seconddigital filters at the beginning of a next processing time interval;means for coupling the transmitted data bit signal received at saidreceiver to the input signal port of both of said first and secondfractionally-spaced equalizers; and means for generating said controlsignal as a function of a most recent bit decision of said transmitteddata bit signal.
 18. The adaptive filter as set forth in claim 17wherein said means for coupling the transmitted data bit signal receivedat said receiver to the input signal port of both of said first andsecond fractionally-spaced equalizers comprises:a matched filter thatfilters the received transmitted data bit signal; a sampling circuitthat samples the received transmitted data bit signal after it haspassed through said matched filter means at a sampling rate that is atleast equal to the Nyquist rate; and means for connecting the sampleddata bit signal to the input signal port of both of said first andsecond fractionally-spaced equalizers.
 19. The adaptive filter as setforth in claim 18 wherein said matched filter has a frequency responseH*(ω) adapted to match the spectrally inefficient, substantiallynon-flat, power spectrum of the transmitted data bit signal.
 20. Theadaptive filter as set forth in claim 19 wherein said means for couplingthe transmitted data bit signal received at said receiver to the inputsignal port of both of said first and second fractionally-spacedequalizers further includes a downconversion circuit for removing an RFcarrier signal from said transmitted data bit signal prior to presentingsaid signal to said matched filter means.
 21. The adaptive filter as setforth in claim 17 further including other filter means A(ω) coupled toreceive the transmitted data bit signal from others of said multiplicityof transmitters, the set of output terminals of said multiplexer circuitbeing coupled to said other filter means, whereby the set of tap signalsselected by said multiplexer circuit may be used to control the responseof said other filter means.
 22. A method of detecting with a maximizedsignal-to-noise ratio (SNR) whether the bits of a transmitted data sgnalused within a code-division multiple access (CDMA) communications systemrepresent a digital "1" or a digital "0", said CDMA communicationssystem including a plurality of transmitters, each of which includesmeans for transmitting data signals at the same data rate and bandwidthas may be transmitted by others of the transmitters at the same time,and a base-station receiver adapted to receive said transmitted datasignals, said method comprising the steps of:(a) generating a sequenceof chip pulses that define a unique chip sequence within each bit timeof the data signal to be transmitted, said unique chip sequence servingto identify a particular transmitter from which the transmitted signaloriginates; (b) shaping the chip pulses of each sequence of chip pulsesgenerated in step (a) so that each has a spectrally inefficient,substantially non-flat, power spectrum within a band ±1/T_(C), whereT_(C) is a chip time between the chip pulses of the sequence of chippulses; (c) transmitting the sequence of chip pulses shaped in step (b)as part of each data bit that is transmitted by the particulartransmitter, whereby each data bit transmitted is encoded with saidunique chip sequence; (d) receiving the sequence of chip pulses at thereceiver; (e) passing the sequence of chip pulses received in step (d)through a matched filter, said matched filter having a frequencyresponse adapted to match the powr spectrum of the transmitted chippulses; (f) sampling the sequence of chip pulses passed through thematched filter in step (e) at a Nyquist rate to produce a sampled seriesof pulses, x_(m) (i); (g) passing the sampled series of pulses, x_(m)(i), through a first fractionally spaced equalizer adapted to produce asequence of pulses y_(m) (i), said first fractionally-spaced equalizerbeing configured to exhibit a frequency response that compensates forthe spectrally inefficient, substantially non-flat shape of the powerspectrum of the transmitted pulses, and to adaptively compensate forsignal distortions that occur in said sequence of chip pulses whileen-route to said receiver, so as to produce a net frequency response forthe series of pulses y_(m) (i) that is substantially flat over allfrequencies of interest, thereby maximizing the SNR of the series y_(m)(i), and that automatically compensates for signal distortions; and (h)determining whether the sequence of pulses y_(m) (i) represents a databit that is a digital "1" or a digital "0".
 23. The method as set forthin claim 22 further including:passing the sampled series of pulses,x_(m) (i), through a second fractionally spaced equalizer adapted toproduce a sequence of pulses y_(m) (i), said second fractionally-spacedequalizer being configured the same as the first fractionally spacedequalizer, each of said first and second fractionally spaced equalizersgenerating a set of tapped weights that are used by said fractionallyspaced equalizer as it converts the sampled series of pulses x_(m) (i)to a sequence of pulses Y_(m) (i); comparing the sequence of pulsesoutput from the first of said fractionally-spaced equalizers with apositive reference sequence of chip pulses, and comparing the sequenceof pulse output from the second of said fractionally-spaced equalizerswith a negative sequence of chip pulses, and determining which of saidfirst or second fractionally-spaced equalizers has more accuratelydetected the bit of the transmitted data signal; and selecting one ofthe set of tap weights generated by said first fractionally spacedequalizer or said second fractionally spaced equalizer for use by bothsaid first and second fractionally spaced equalizers when processing anext bit of the transmitted data signal as a function of which of saidfirst or second fractionally spaced equalizers accurately detected thecurrent bit of the transmitted data signal.